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1 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram 2 meg x 32 configuration 512k x 32 x 4 banks refresh count 4k row addressing 2k (a0-a10) bank addressing 4 (ba0, ba1) column addressing 256 (a0-a7) pin assignment (top view) 86-pin tsop features ? pc100 functionality fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst lengths: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge, and auto refresh modes self refresh mode 64ms, 4,096-cycle refresh (15.6s/row) lvttl-compatible inputs and outputs single +3.3v 0.3v power supply supports cas latency of 1, 2, and 3 options marking configuration 2 meg x 32 (512k x 32 x 4 banks) 2m32b2 plastic package - ocpl 1 86-pin tsop (400 mil) tg timing (cycle time) 5ns (200 mhz) -5 5.5ns (183 mhz) -55 6ns (166 mhz) -6 7ns (143 mhz) -7 operating temperature range commercial (0 to +70c) none extended (-40c to +85c) it 2 note: 1. off-center parting line 2. available on -7 part number example: MT48LC2M32B2tg-7 note: the # symbol indicates signal is active low. v dd dq 0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v dd dqm0 we# cas# ras# cs# nc ba0 ba1 a10 a0 a1 a2 dqm2 v dd nc dq16 v ss q dq17 dq18 v dd q dq19 dq20 v ss q dq21 dq22 v dd q dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v dd q dq30 dq29 v ss q dq28 dq27 v dd q dq26 dq25 v ss q dq24 v ss synchronous dram MT48LC2M32B2 - 512k x 32 x 4 banks for the latest data sheet, please refer to the micron web site: www.micron.com/ sdramds key timing parameters speed clock access time setup hold grade frequency cl = 3* time time -5 200 mhz 4.5ns 1.5ns 1ns -55 183 mhz 5ns 1.5ns 1ns -6 166 mhz 5.5ns 1.5ns 1ns -7 143 mhz 5.5ns 2ns 1ns *cl = cas (read) latency
2 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst se- quence. the 64mb sdram uses an internal pipelined archi- tecture to achieve high-speed operation. this archi- tecture is compatible with the 2 n rule of prefetch archi- tectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while ac- cessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. the 64mb sdram is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdrams offer substantial advances in dram oper- ating performance, including the ability to synchro- nously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. general description the 64mb sdram is a high-speed cmos, dynamic random-access memory containing 67,108,864-bits. it is internally configured as a quad-bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registra- tion of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank, a0-a10 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. 64mb (x32) sdram part number part number architecture MT48LC2M32B2tg 2 meg x 32
3 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram table of contents functional block diagram - 2 meg x 32 ................. 4 pin descriptions ..................................................... 5 functional description ......................................... 6 initialization ...................................................... 6 register definition ............................................ 6 mode register ............................................... 6 burst length ............................................ 6 burst type ............................................... 7 cas latency ............................................ 8 operating mode ...................................... 8 write burst mode .................................... 8 commands ............................................................ 9 truth table 1 (commands and dqm operation) ............ 9 command inhibit ............................................. 10 no operation (nop) .......................................... 10 load mode register ........................................... 10 active ................................................................ 10 read ................................................................ 10 write ................................................................ 10 precharge ........................................................... 10 auto precharge .................................................. 10 burst terminate ................................................. 11 auto refresh ...................................................... 11 self refresh ........................................................ 11 operation ............................................................... 12 bank/row activation ........................................ 12 reads ................................................................ 13 writes ................................................................ 19 precharge ........................................................... 21 power-dow n ...................................................... 21 clock suspend .................................................. 22 burst read/single write .................................... 22 concurrent auto precharge .............................. 23 write with auto precharge ............................... 24 truth table 2 (cke) ................................................ 25 truth table 3 (current state, same bank) ..................... 26 truth table 4 (current state, different bank) ................. 28 absolute maximum ratings .................................. 30 dc electrical characteristics and operating conditions ...................................... 30 i dd specifications and conditions ......................... 30 capacitance ............................................................ 32 ac electrical characteristics (timing table) .... 32 ac electrical characteristics ................................... 34 timing waveforms initialize and load mode register .................... 36 power-down mode .......................................... 37 clock suspend mode ........................................ 38 auto refresh mode ........................................... 39 self refresh mode ............................................. 40 reads read ? single read ....................................... 41 read ? without auto precharge ................. 42 read ? with auto precharge ....................... 43 alternating bank read accesses .................. 44 read ? full-page burst ................................. 45 read ? dqm operation .............................. 46 writes write ? single write ..................................... 47 write ? without auto precharge ................ 48 write ? with auto precharge ...................... 49 alternating bank write accesses ................. 50 write ? full-page burst ................................ 51 write ? dqm operation ............................. 52
4 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram functional block diagram 2 meg x 32 sdram 11 ras# cas# clk cs# we# cke 8 a0-a10, ba0, ba1 dqm0- dqm3 13 256 (x32) 8192 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (2,048 x 256 x 32) bank0 row- address latch & decoder 2048 sense amplifiers bank control logic dq0- dq31 32 32 data input register data output register 32 bank1 bank0 bank2 bank3 11 8 2 4 4 2 refresh counter 11 11 mode register control logic command decode row- address mux address register column- address counter/ latch
5 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram pin descriptions pin numbers symbol type description 68 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 67 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank) or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. 20 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 17, 18, 19 we#, cas#, input command inputs: we# , cas#, and ras# (along with cs#) define the ras# command being entered. 16, 71, 28, 59 dqm0- input input/output mask: dqm is sampled high and is an input mask signal dqm3 for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) during a read cycle. dqm0 corresponds to dq0- dq7; dqm1 corresponds to dq8-dq15; dqm2 corresponds to dq16-dq23; and dqm3 corresponds to dq24-dq31. dqm0-dqm3 are considered same state when referenced as dqm. 22, 23 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. 25-27, 60-66, 24 a0-a10 input address inputs: a0-a10 are sampled during the active command (row- address a0-a10) and read/write command (column-address a0-a7 with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, dq0-dq31 input/ data i/os: data bus. 74, 76, 77, 79, 80, 82, 83, output 85, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56 14, 21, 30, 57, 69, 70, 73 nc ? no connect: these pins should be left unconnected. pin 70 is reserved for sstl reference voltage supply. 3, 9, 35, 41, 49, 55, 75, 81 v dd q supply dq power supply: isolated on the die for improved noise immunity. 6, 12, 32, 38, 46, 52, 78, 84 v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. 1, 15, 29, 43 v dd supply power supply: +3.3v 0.3v. (see note 27 on page 35.) 44, 58, 72, 86 v ss supply ground.
6 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram functional description in general, this 64mb sdram (512k x 32 x 4 banks) is a quad-bank dram that operates at 3.3v and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32-bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registra- tion of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-a10 select the row). the address bits (a0-a7) registered coincident with the read or write command are used to select the starting col- umn location for the burst access. prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register defini- tion, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to v dd and v dd q (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command hav- ing been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition in- cludes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 1. the mode register is programmed via the load mode register command and will re- tain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 is reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 1. the burst length determines the maximum number of column locations that can be ac- cessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full- page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively se- lected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely se- lected by a1-a7 when the burst length is set to two; by a2-a7 when the burst length is set to four; and by a3-a7 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached.
7 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram note: 1. for a burst length of two, a1-a7 select the block- of-two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2-a7 select the block- of-four burst; a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a7 select the block- of-eight burst; a0-a2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0-a7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0-a7 select the unique column to be accessed, and mode register bit m3 is ignored. table 1 burst definition burst starting column order of accesses within a burst length addres s type = sequential type = interleaved a0 2 00-1 0-1 11-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a7 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (256) (location 0 -256) ?cn - 1, cn? figure 1 mode register definition burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 1. 000 001 010 011 100 101 110 111 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleave cas latency reserved 1 2 3 reserved reserved reserved reserved 000 001 010 011 100 101 110 111 burst length m0 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 m2 m3 m4 m5 m6 m6 - m0 m8 m7 op mode a10 10 reserved* wb 0 1 write burst mode programmed burst length single location access m9 1. *should program a10, ba0, and ba1= ?0? to ensure compatibility with future device
8 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram allowable operating frequency (mhz) cas cas cas speed latency = 1 latency = 2 latency = 3 - 5 - - 200 -55 - - 183 - 6 50 100 166 - 7 50 100 143 reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. cas latency the cas latency is the delay, in clock cycles, be- tween the registration of a read command and the availability of the first piece of output data. the la- tency can be set to one, two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. table 2 below indicates the operat- ing frequencies at which each cas latency setting can be used. figure 2 cas latency table 2 cas latency clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
9 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram truth table 1 ? commands and dqm operation (note: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or self refresh l l l h x x x 6, 7 (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable ????l ? a ctive 8 write inhibit/output high-z ????h ? high-z 8 appear following the operation section; these tables provide current state/next state information. commands truth table 1 provides a quick reference of avail- able commands. this is followed by a written descrip- tion of each command. three additional truth tables note: 1. cke is high for all commands shown except self refresh. 2. a0-a10 define the op-code written to the mode register. 3. a0-a10 provide row address, ba0 and ba1 determine which bank is made active. 4. a0-a7 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0 and ba1 determine which bank is being read from or written to. 5. a10 low: ba0 and ba1 determine the bank being precharged. a10 high: all banks precharged and ba0 and ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). dqm0 controls dq0-dq7; dqm1 controls dq8-dq15; dqm2 controls dq16-dq23; and dqm3 controls dq24-dq31.
10 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram command inhibit the command inhibit function prevents new commands from being executed by the sdram, re- gardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-a10. see mode register heading in the register definition sec- tion. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a0-a10 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before open- ing a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0 and ba1 (b1) inputs selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqmx signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqmx signal was regis- tered low, the corresponding dqs will provide valid data. dqm0 corresponds to dq0-dq7, dqm1 corre- sponds to dq8-dq15, dqm2 corresponds to dq16- dq23 and dqm3 corresponds to dq24-dq31. write the write command is used to initiate a burst write access to an active row. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coinci- dent with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the correspond- ing data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0 and ba1 select the bank. otherwise ba0 and ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function de- scribed above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is ad- dressed with the read or write command is auto- matically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is non- persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet.
11 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram burst terminate the burst terminate command is used to trun- cate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in the operation section of this data sheet. auto refresh auto refresh is used during normal operation of the sdram and is analagous to cas#-before-ras# (cbr) refresh in conventional drams. this com- mand is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 64mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref), regardless of width option. providing a distributed auto refresh command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rc), once every 64ms. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram pro- vides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefi- nite period beyond that. the procedure for exiting self refresh requires a se- quence of commands. first, clk must be stable (stable clock is defined as a signal cycling within timing con- straints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of any internal refresh in progress. upon exiting self refresh mode, auto refresh commands must be issued every 15.625ms or less as both self refresh and auto refresh utililze the row refresh counter.
12 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram operation bank/row activation before any read or write commands can be is- sued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the ac- tive command, which selects both the bank and the row to be activated. see figure 3. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be issued. for example, a t rcd specifi- cation of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 4, which covers any case where 2 < t rcd (min)/ t ck - 3. (the same procedure is used to convert other specifi- cation limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 4 example: meeting t rcd (min) when 2 < t rcd (min)/ t ck - 3 clk t2 t1 t3 t0 t command nop active read or write nop rcd (min) t rcd (min) = 20ns, t ck = 8ns t rcd (min) x t ck where x = number of clocks for equation to be true. t rcd (min) +0.5 t ck t ck t ck t ck don?t care figure 3 activating a specific row in a specific bank cs# we# cas# ras# cke clk a0?a10 row address high ba0, ba1 bank address
13 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram upon completion of a burst, assuming no other com- mands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a subsequent read command, and data from a fixed- length read burst may be immediately followed by data from a read command. in either case, a continu- ous flow of data can be maintained. the first data ele- ment from the new burst follows either the last ele- ment of a completed burst or the last desired data ele- ment of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 7 for cas latencies of one, two and reads read bursts are initiated with a read command, as shown in figure 5. the starting column and bank addresses are pro- vided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the ge- neric read commands used in the following illustra- tions, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 6 shows general timing for each possible cas latency setting. figure 5 read command figure 6 cas latency clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop cs# we# cas# ras# cke clk column address a0?a7 a10 ba0, 1 high enable auto precharge disable auto precharge bank address a8, a9
14 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. this 64mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any figure 7 consecutive read bursts clock cycle following a previous read command. full- speed random read accesses can be performed to the same bank, as shown in figure 8, or each subsequent read may be performed to a different bank. clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles note: each read command may be to either bank. dqm is low. cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3 don?t care
15 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram figure 8 random read accesses clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read note: each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3
16 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram data from any read burst may be truncated with a subsequent write command, and data from a fixed- length read burst may be immediately followed by data from a write command (subject to bus turn- around limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be a possibility that the device driv- ing the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. figure 10 read to write with extra clock cycle figure 9 read to write don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck note: a cas latency of three is used for illustration. the read command ma y be to an y bank , and the write command the dqm input is used to avoid i/o contention, as shown in figures 9 and 10. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buff- ers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal; provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in fig- ure 10, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 9 shows the case where the clock frequency al- lows for bus contention to be avoided without adding a nop cycle, and figure 10 shows the case where the additional nop is needed.
17 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram figure 11 read to precharge a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti- vated), and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles be- fore the clock edge at which the last desired data ele- ment is valid, where x equals the cas latency minus one. this is shown in figure 11 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a , col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a , row bank ( a or all) don?t care x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) x = 2 cycles
18 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram figure 12 terminating a read burst operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the com- mand and address buses be available at the appropri- ate time to issue the command; the advantage of the precharge command is that it can be used to trun- cate fixed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not acti- vated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 12 for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles
19 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram writes write bursts are initiated with a write command, as shown in figure 13. the starting column and bank addresses are pro- vided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the ge- neric write commands used in the following illustrations,auto precharge is disabled. during write bursts, the first valid data-in ele- ment will be registered coincident with the write com- mand. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 14). a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data for any write burst may be truncated with a subsequent write command, and data for a fixed- length write burst may be immediately followed by data for a write command. the new write command figure 15 write to write can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. an ex- ample is shown in figure 15. data n + 1 is either the last of a burst of two or the last desired of a longer burst. this 64mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a write command can be initi- ated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 16, or each subsequent write may be per- formed to a different bank. clk dq d in n t2 t1 t3 t0 command address nop nop write d in n + 1 nop bank, col n figure 14 write burst cs# we# cas# ras# cke clk column address high enable auto precharge disable auto precharge bank address a0?a7 a10 ba0, 1 a8, a9 figure 13 write command clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b note: dqm is low. each write command may be to any bank. don?t care
20 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram quency, in auto precharge mode. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge com- mand. an example is shown in figure 18. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. the precharge will actually be- gin coincident with the clock-edge (t2 in figure 18) on a ?one-clock? t wr and sometime between the first and second clock on a ?two-clock? t wr (between t2 and t3 in figure 18.) in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the com- mand and address buses be available at the appropri- ate time to issue the command; the advantage of the precharge command is that it can be used to trun- cate fixed-length or full-page bursts. figure 18 write to precharge data for any write burst may be truncated with a subsequent read command, and data for a fixed- length write burst may be immediately followed by a read command. once the read command is regis- tered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 17. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be fol- lowed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the ?two-clock? write-back requires at least one clock plus time, regardless of fre- figure 17 write to read don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 figure 16 random write cycles don?t car e clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m note: each write command ma y be to an y bank. dqm is low. don?t care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr note: dqm could remain low in this example if the write burst is a fixed length of two. bank a , row t6 nop nop t wr = 2 clk (when t wr > t ck) t wr = 1 clk ( t ck > t wr)
21 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram fixed-length or full-page write bursts can be trun- cated with the burst terminate command. when truncating a write burst, the input data applied coin- cident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 19, where data n is the last desired data element of a longer burst. figure 21 power-down don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) figure 20 precharge command figure 19 terminating a write burst clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) note: dqms are low. precharge the precharge command (figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) af- ter the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0 and ba1 select the bank. when all banks are to be precharged, inputs ba0 and ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit when no ac- cesses are in progress (see figure 21). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. entering power-down deacti- vates the input and output buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). cs# we# cas# ras# cke clk a10 high all banks bank selected a0?a9 ba0, 1 bank address
22 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 figure 22 clock suspend during write burst don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 note: for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. cke internal clock nop figure 23 clock suspend during read burst clock suspend the clock suspend mode occurs when a column ac- cess/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the in- put pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in fig- ures 22 and 23.) clock suspend mode is exited by registering cke high; the internal clock and related operation will re- sume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the pro- grammed burst length and sequence, just as in the normal mode of operation (m9 = 0).
23 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram concurrent auto precharge an access command to (read or write) another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. micron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is regis- tered (figure 24). 2. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (fig- ure 25). clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop note: dqm is low. bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) figure 24 read with auto precharge interrupted by a read clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm note: 1. dqm is high at t2 to prevent d out - a +1 from contending with d in - d at t4. bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care figure 25 read with auto precharge interrupted by a write
24 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address note: 1. dqm is low. bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n figure 26 write with auto precharge interrupted by a read don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop note: 1. dqm is low. bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m figure 27 write with auto precharge interrupted by a write write with auto precharge 3. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out ap- pearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 4. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data regis- tered one clock prior to a write to bank m (figure 27).
25 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram truth table 2 ? cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend l h power-down command inhibit or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibit or nop power-down entry all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see truth table 3 note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1 .
26 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram truth table 3 ? current state bank n , command to bank n (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) l l h h active (select and activate row) idle l l l h auto refresh 7 llll load mode register 7 l l h l precharge 11 l h l h read (select column and start read burst) 10 row active l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read l h l h read (select column and start new read burst) 10 (auto l h l l write (select column and start write burst) 10 precharge l l h l precharge (truncate read burst, start precharge) 8 disabled) l h h l burst terminate 9 write l h l h read (select column and start read burst) 10 (auto l h l l write (select column and start new write burst) 10 precharge l l h l precharge (truncate write burst, start precharge) 8 disabled) l h h l burst terminate 9 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts w ith registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
27 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram note (continued): write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
28 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram truth table 4 ? current state bank n , command to bank m (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row l l h h active (select and activate row) activating, l h l h read (select column and start read burst) 7 active, or l h l l write (select column and start write burst) 7 precharging l l h l precharge read l l h h active (select and activate row) (auto l h l h read (select column and start new read burst) 7, 10 precharge l h l l write (select column and start write burst) 7, 11 disabled) l l h l precharge 9 write l l h h active (select and activate row) (auto l h l h read (select column and start read burst) 7, 12 precharge l h l l write (select column and start new write burst) 7, 13 disabled) l l h l precharge 9 read l l h h active (select and activate row) (with auto l h l h read (select column and start new read burst) 7, 8, 14 precharge) l h l l write (select column and start write burst) 7, 8, 15 l l h l precharge 9 write l l h h active (select and activate row) (with auto l h l h read (select column and start read burst) 7, 8, 16 precharge) l h l l write (select column and start new write burst) 7, 8, 17 l l h l precharge 9 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
29 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram note (continued): 4. auto refresh, self refresh, and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later (figure 7). 11. for a read without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figures 9 and 10). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (figure 17), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 13. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered (figure 15). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency la ter. the precharge to bank n will begin when the read to bank m is registered (figure 24). 15. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contenti on. the precharge to bank n will begin when the write to bank m is registered (figure 25). 16. for a write with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 17. for a write with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock prior to the write to bank m (figure 27).
30 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram absolute maximum ratings* voltage on v dd , v dd q supply relative to v ss .............................................. -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss .............................................. -1v to +4.6v operating temperature, t a ............................ 0c to +70c extended temperature .......................... -40c to +85c storage temperature (plastic) ............ -55c to +150c power dissipation ........................................................ 1w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 6, 27; notes appear on page 35) (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd , v dd q 3 3.6 v 27 input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd i i -5 5 a (all other pins not under test = 0v) output leakage current: dqs are disabled; 0v v out v dd qi oz -5 5 a output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ?0.4v
31 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram i dd specifications and conditions (notes: 1, 6, 11, 13, 27; notes appear on page 35) (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol -5 -55 units notes operating current: active mode; i dd 1 200 190 ma 3, 18, burst = 2; read or write; t rc = t rc (min); 19, 26 cas latency = 3 standby current: power-down mode; i dd 2 22ma cke = low; all banks idle standby current: active mode; cs# = high; i dd 3 80 70 ma 3, 12, cke = high; all banks active after t rcd met; 19, 26 no accesses in progress operating current: burst mode; continuous burst; i dd 4 280 260 ma 3, 18, read or write; all banks active, 19, 26 cas latency = 3 auto refresh current: t rfc = t rfc (min) i dd 5 225 225 ma 3, 12, cas latency = 3; cke, cs# = high 18, 19, 26, 29 self refresh current: cke 0.2v i dd 6 22ma4 max i dd specifications and conditions (notes: 1, 6, 11, 13, 27; notes appear on page 35) (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol -6 -7 units notes operating current: active mode; i dd 1 150 130 ma 3, 18, burst = 2; read or write; t rc = t rc (min); 19, 26 cas latency = 3 standby current: power-down mode; i dd 2 22ma cke = low; all banks idle standby current: active mode; cs# = high; i dd 3 60 50 ma 3, 12, cke = high; all banks active after t rcd met; 19, 26 no accesses in progress operating current: burst mode; continuous burst; i dd 4 180 160 ma 3, 18, read or write; all banks active, 19, 26 cas latency = 3 auto refresh current: t rfc = t rfc (min) i dd 5 225 225 ma 3, 12, cas latency = 3; cke, cs# = high 18, 19, 26, 29 self refresh current: cke 0.2v i dd 6 22ma4 max
32 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram electrical characteristics and recommended ac operating conditions (notes: 5, 6, 8, 9, 11; notes appear on page 35) ac characteristics -5 -55 parameter symbol min max min max units notes access time from clk cl = 3 t ac (3) 4.5 5 ns (pos. edge) cl = 2 t ac (2) - - ns cl = 1 t ac (1) - - ns address hold time t ah 1 1 ns address setup time t as 1.5 1.5 ns clk high-level width t ch 2 2 ns clk low-level width t cl 2 2 ns clock cycle time cl = 3 t ck (3) 5 5.5 ns 23 cl = 2 t ck (2) - - ns 23 cl = 1 t ck (1) - - ns 23 cke hold time t ckh 1 1 ns cke setup time t cks 1.5 1.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 ns data-in hold time t dh 1 1 ns data-in setup time t ds 1.5 1.5 ns data-out high-impedance time cl = 3 t hz (3) 4.5 5 ns 10 cl = 2 t hz (2) - - ns 10 cl = 1 t hz (1) - - ns 10 data-out low-impedance time t lz 1 1 ns data-out hold time t oh 1.5 2 ns active to precharge command t ras 38.7 120k 38.7 120k ns active to active command period t rc 55 55 ns auto refresh period t rfc 60 60 ns active to read or write delay t rcd 15 16.5 ns refresh period (4,096 rows) t ref 64 64 ms precharge command period t rp 15 16.5 ns active bank a to active bank b command t rrd 10 11 ns 25 transition time t t 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 2 2 t ck 24 exit self refresh to active command t xsr 55 55 ns 20 capacitance (note: 2; notes appear on page 35) parameter symbol min max units input capacitance: clk c i 1 2.5 4.0 p f input capacitance: all other input-only pins c i 2 2.5 4.0 p f input/output capacitance: dqs c io 4.0 6.5 p f
33 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram electrical characteristics and recommended ac operating conditions (notes: 5, 6, 8, 9, 11; notes appear on page 35) ac characteristics -6 -7 parameter symbol min max min max units notes access time from clk cl = 3 t ac (3) 5.5 5.5 ns (pos. edge) cl = 2 t ac (2) 7.5 8 ns cl = 1 t ac (1) 17 17 ns address hold time t ah 1 1 ns address setup time t as 1.5 2 ns clk high-level width t ch 2.5 2.75 ns clk low-level width t cl 2.5 2.75 ns clock cycle time cl = 3 t ck (3) 6 7 ns 23 cl = 2 t ck (2) 10 10 ns 23 cl = 1 t ck (1) 20 20 ns 23 cke hold time t ckh 1 1 ns cke setup time t cks 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 2 ns data-in hold time t dh 1 1 ns data-in setup time t ds 1.5 2 ns data-out high-impedance time cl = 3 t hz (3) 5.5 5.5 ns 10 cl = 2 t hz (2) 7.5 8 ns 10 cl = 1 t hz (1) 17 17 ns 10 data-out low-impedance time t lz 1 1 ns data-out hold time t oh 2 2.5 ns active to precharge command t ras 42 120k 42 120k ns active to active command period t rc 60 70 ns auto refresh period t rfc 60 70 ns active to read or write delay t rcd 18 20 ns refresh period (4,096 rows) t ref 64 64 ms precharge command period t rp 18 20 ns active bank a to active bank b command t rrd 12 14 ns 25 transition time t t 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1clk+ 1clk+ t ck 24 6ns 7ns 12ns 14ns ns 28 exit self refresh to active command t xsr 70 70 ns 20
34 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram ac functional characteristics (notes: 5, 6, 7, 8, 9, 11; notes appear on page 35) parameter symbol -5 -55 -6 -7 units notes read/write command to read/write command t ccd 1111 t ck 17 cke to clock disable or power-down entry mode t cked 1111 t ck 14 cke to clock enable or power-down exit setup mode t ped 1111 t ck 14 dqm to input data delay t dqd 0000 t ck 17 dqm to data mask during writes t dqm 0000 t ck 17 dqm to data high-impedance during reads t dqz 2222 t ck 17 write command to input data delay t dwd 0000 t ck 17 data-in to active command cl = 3 t dal (3) 5555 t ck 15, 21 cl = 2 t dal (2) - - 4 4 t ck 15, 21 cl = 1 t dal (1) - - 3 3 t ck 15, 21 data-in to precharge command t dpl 2222 t ck 16, 21 last data-in to burst stop command t bdl 1111 t ck 17 last data-in to new read/write command t cdl 1111 t ck 17 last data-in to precharge command t rdl 2222 t ck 16, 21 load mode register command to active or refresh command t mrd 2222 t ck 26 data-out to high-impedance from precharge command cl = 3 t roh (3) 3333 t ck 17 cl = 2 t roh (2) - - 2 2 t ck 17 cl = 1 t roh (1) - - ? 1 t ck 17
35 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram 13. i dd specifications are tested after the device is prop- erly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times dur- ing this period. 21. based on t ck = 143 mhz for -7, 166 mhz for -6, 183 mhz for -55, and 200 mhz for -5. 22. v ih overshoot: v ih (max) = v dd q + 1.2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -1.2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 23. the clock frequency must remain constant during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. 25. jedec and pc100 specify three clocks. 26. t ck = 7ns for -7, 6ns for -6, 5.5ns for -5.5, and 5ns for -5. 27. v dd (min) = 3.135v for -6, -55, and -5 speed grades. 28. check factory for availability of specially screened devices having t wr = 10ns. t wr = 1 t ck for 100 mhz and slower ( t ck = 10ns and higher) in manual precharge. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. ac can range from 0pf to 6pf. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indi- cate cycle time at which proper operation over the full temperature range (0c t a + 70c and -40c t a + 85c for it parts) is ensured. 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = .25 and v ih = 2.75, with timing referenced to 1.5v crossover point. 12. other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid v ih or v il levels. q 30p f
36 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram initialize and load mode register *cas latency indicated in parentheses. note: 1. the mode register may be loaded prior to the auto refresh cycles if desired. 2. outputs are guaranteed high-z after command is issued. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t mrd222 t ck t r f c 60 60 70 n s t rp 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t clk (3) 5 6 7 ns t clk (2) 10 10 ns t clk (1) 20 20 ns t ch t cl t ck cke clk command dq ba0, ba1 bank t rfc t mrd t rfc auto refresh auto refresh program mode register 1, 2, 5 t cmh t cms precharge all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) t cks power-up: v dd and ck stable t = 100s (min) precharge nop auto refresh nop load mode register active nop nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) auto refresh all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ckh ( ) ( ) ( ) ( ) dqm 0-3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t cmh t cms t cmh t cms a0-a9 row t ah t as code t ah t as code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a10 row t ah t as code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks single bank ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care undefined t0 t1 tn + 1 to + 1 tp + 1 tp + 2 tp + 3
37 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram note: 1. violating refresh requirements during power-down may result in a loss of data. power-down mode 1 *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ck (1) 20 20 ns t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm 0-3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0-a9 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 don?t care undefined
38 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram clock suspend mode 1 note: 1. for this example, the burst length = 2, the cas latency = 3, and auto precharge is disabled. 2. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t dh111ns t ds 1.5 1.5 2 ns t hz (3) 4.5 5.5 5.5 ns t hz (2) ? 7.5 8 ns t hz (1) ? 17 17 ns t lz111ns t oh 1.5 2 2.5 ns timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.5 5.5 5.5 ns t ac (2) 7.5 8 ns t ac (1) 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) ? 10 10 ns t ck (1) ? 20 20 ns t ckh 1 1 1 ns t ch t cl t ck t ac t lz dqm0-3 clk dq a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d out e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write don?t care undefined cke t cks t ckh bank column m t ds d out e + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ba0, ba1 a0-a9
39 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram auto refresh mode *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t r f c 60 60 70 n s t rp 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns undefined don?t care t ch t cl t ck cke clk dq t rfc ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t rfc high-z bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 ba0, ba1 a0?a9 dqm 0?3 don?t care
40 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram self refresh mode *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rp 15 18 20 n s t xsr 55 70 70 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) don?t care undefined command t cmh t cms auto refresh precharge nop nop bank(s) high-z t cks ah as auto refresh > t ras t ckh t cks t t t cks all banks single bank a10 t0 t1 t2 tn + 1 to + 1 to + 2 ba0, ba1 dqm 0-3 a0-a9 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
41 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram single read 1 *cas latency indicated in parentheses. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm / dqml, dqmh cke clk a0-a9 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank bank row row bank t hz command t cmh t cms precharge active nop read nop active disable auto precharge single bank t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 don?t care note: 1. for this example, the burst length = 1, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a8, a9 = ?don?t care.? timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.5 5.5 5.5 ns t ac (2) - 7.5 8 ns t ac (1) - 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) - 10 10 ns t ck (1) - 20 20 ns t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t hz (3) 4.5 5.5 5.5 ns t hz (2) - 7.5 8 ns t hz (1) - 17 17 ns t lz111ns t oh 1.5 2 2.5 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s -5 -6 -7 symbol* min max min max min max units
42 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram read ? without auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t cmh111ns t cms 1.5 1.5 2 ns t hz (3) 4.5 5.5 5.5 ns t hz (2) - 7.5 8 ns t hz (1) - 17 17 ns t lz111ns t oh 1.5 2 2.5 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.5 5.5 5.5 ns t ac (2) - 7.5 8 ns t ac (1) - 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) - 10 10 ns t ck (1) - 20 20 ns t ckh 1 1 1 ns t cks 1.5 1.5 2 ns all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single bank don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0-a9
43 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram read ? with auto precharge 1 don?t care undefined enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc cke clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0-a9 note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t cmh111ns t cms 1.5 1.5 2 ns t hz (3) 4.5 5.5 5.5 ns t hz (2) - 7.5 8 ns t hz (1) - 17 17 ns t lz111ns t oh 1.5 2 2.5 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.5 5.5 5.5 ns t ac (2) - 7.5 8 ns t ac (1) - 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) - 10 10 ns t ck (1) - 20 20 ns t ckh 1 1 1 ns t cks 1.5 1.5 2 ns
44 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram alternating bank read accesses 1 note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t lz111ns t oh 1.5 2 2.5 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s t r r d 10 12 14 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.5 5.5 5.5 ns t ac (2) - 7.5 8 ns t ac (1) - 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) - 10 10 ns t ck (1) - 20 20 ns t ckh 1.5 1 1 ns don?t care undefined enable auto precharge t ch t cl t ck t ac t lz clk dq a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 4 bank 4 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 4 cas latency - bank 4 t t rc - bank 0 rrd ba0, ba1 dqm 0-3 a0-a9
45 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram read ? full-page burst 1 note: 1. for this example, the cas latency = 2. 2. a8 and a9 = ?don?t care.? 3. page left open; no t rp. *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t hz (3) 4.5 5 5.5 ns t hz (2) - 7.5 8 ns t hz (1) - 17 17 ns t lz111ns t oh 1.5 2 2.5 ns t r c d 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.5 5.5 5.5 ns t ac (2) - 7.5 8 ns t ac (1) - 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) - 10 10 ns t ck (1) - 20 20 ns t ch t cl t ck t ac t lz t rcd cas latency cke clk dq a10 t oh dout m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 256 locations within same row don?t care undefined command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 ba0, ba1 dqm 0-3 a0-a9
46 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram read ? dqm operation 1 t ch t cl t ck t rcd cas latency cke clk dq a10 t cms row bank row bank don?t care undefined t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 ba0, ba1 dqm 0-3 a0-a9 note: 1. for this example, the cas latency = 2. 2. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t hz (3) 4.5 5 5.5 ns t hz (2) - 7.5 8 ns t hz (1) - 17 17 ns t lz111ns t oh 1.5 2 2.5 ns t r c d 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ac (3) 4.6 5.5 5.5 ns t ac (2) - 7.5 8 ns t ac (1) - 17 17 ns t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) - 10 10 ns t ck (1) - 20 20 ns
47 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram single write timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 1.5 2 ns t dh111ns t ds 1.5 1.5 2 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s t wr 2 t c k 12 14 n s *cas latency indicated in parentheses. don?t care disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqm / dqml, dqmh cke clk a0-a9 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms active nop write nop precharge active t ah t as t ah t as single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 nop -5 -6 -7 symbol* min max min max min max units note: 1. for this example, the burst length = 4, and the write burst is followed by a ?manual? precharge. 2. 10ns is required between and the precharge command, regardless of frequency, to meet t wr. 3. a8, a9 = ?don?t care.?
48 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram write ? without auto precharge 1 note: 1. for this example, the burst length = 4, and the write burst is followed by a ?manual? precharge. 2. faster frequencies require two clocks (when t wr > t ck). 3. a8 and a9 = ?don?t care.? 4. t wr of 1 clk available if running 100 mhz or slower. check factory for availability. *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t cmh111ns t cms 1.5 1.5 2 ns t dh111ns t ds 1.5 1.5 2 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s t wr 4 2 t c k 12 14 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns t ckh 1 1 1 ns t cks 1.5 2 2 ns disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop precharge active t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 dqm 0-3 ba0, ba1 a0-a9
49 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram t cms 1.5 1.5 2 ns t dh111ns t ds 1.5 1.5 2 ns t ras 38.7 120,000 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s t wr 2 t ck 1 clk+ 1 clk+ ns 67 write ? with auto precharge 1 note: 1. for this example, the burst length = 4. 2. faster frequencies require two clocks (when t wr > t ck). 3. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns t ckh 1 1 1 ns t cks 1.5 2 2 ns t cmh 1 1 1 ns don?t care enable auto precharge t ch t cl t ck t rp t ras t rcd t rc cke clk dq a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 ba0, ba1 dqm 0-3 a0-a9
50 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram alternating bank write accesses 1 t ch t cl t ck clk dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqm / dqml, dqmh a0-a9 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 2 column m 2 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 note: 1. for this example, the burst length = 4. 2. faster frequencies require two clocks (when t wr > t ck). 3. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t dh111ns t ds 1.5 1.5 2 ns t ras 38.7 42 120,000 42 120,000 ns t rc 55 60 70 n s t r c d 15 18 20 n s t rp 15 18 20 n s t r r d 10 12 14 n s t wr 2 t ck 1 clk+ 1 clk+ ns 67 timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns t ckh 1 1 1 ns t cks 1.5 2 2 ns t cmh111ns t cms 1.5 1.5 2 ns
51 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram write ? full-page burst note: 1. a8 and a9 = ?don?t care.? 2. t wr must be satisfied prior to precharge command. 3. page left open; no t rp. *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 1.5 2 ns t cmh111ns t cms 1.5 2 2 ns t dh111ns t ds 1.5 1.5 2 ns t r c d 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns t ch t cl t ck t rcd cke clk a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 256 locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 ba0, ba1 dqm 0-3 a0-a9
52 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram write ? dqm operation 1 note: 1. for this example, the burst length = 4. 2. a8 and a9 = ?don?t care.? *cas latency indicated in parentheses. -5 -6 -7 symbol* min max min max min max units t ckh 1 1 1 ns t cks 1.5 2 2 ns t cmh111ns t cms 1.5 1.5 2 ns t dh111ns t ds 1.5 1.5 2 ns t r c d 15 18 20 n s timing parameters -5 -6 -7 symbol* min max min max min max units t ah111ns t as 1.5 1.5 2 ns t ch 2 2.5 2.75 ns t cl 2 2.5 2.75 ns t ck (3) 5 6 7 ns t ck (2) 10 10 ns t ck (1) 20 20 ns don?t care t ch t cl t ck t rcd cke clk dq a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7 ba0, ba1 dqm 0-3 a0-a9
53 64mb: x32 sdram micron technology, inc., reserves the right to change products or specifications without notice. 64msdramx32_5.p65 ? rev. b; pub. 6/02 ?2002, micron technology, inc. 64mb: x32 sdram 86-pin plastic tsop (400 mil) see detail a r 1.00 (2x) r .75 (2x) .50 typ .61 10.16 .08 .50 .10 11.76 .10 pin #1 id detail a 22.22 .08 0.20 +.07 -.03 .15 +.03 -.02 .10 +.10 -.05 1.20 max .10 .25 guage plane .80 typ .10 (2x) 2.80 (2x) note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.025mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron and the m logo are registered trademarks and the micron logo is a trademark of micron technology, inc.

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